Invitation to Bid – FPGA Development and Evaluation Board in CHENNAI, TAMIL NADU
Public procurement opportunity for N/aFPGA Development and Evaluation Board (Q3) in CHENNAI, TAMIL NADU. Quantity: 1 issued by . Submission Deadline: 15-09-2025 18:00:00. View full details and respond.
Goods
Qty: 1
Financial
EMD Amount:₹29,980.00
OEM Avg Turnover:₹7.00 Lakh (s)
Minimum Turnover:₹7.00 Lakh (s)
Bid Offer Validity:30 (Days)
Past Performance:50 %
Arbitration Clause:No
Mediation Clause:No
Technical
Evaluation Method:Total value wise evaluation
Inspection Required:Yes
Technical Clarifications Time:2 Days
Timeline
Issue
September 3, 2025 at 5:55 PM
Bid deadline: September 15, 2025 at 6:00 PM
Bid Opening
15-09-2025 18:30:00
Bid opening: 15-09-2025 18:30:00
Bid Opening Information
Bid Opening Date:15-09-2025 18:30:00
Tender Configuration
Bid Type
Goods
Tender Documents
4 DocumentsDocuments Required from Seller
- Experience Criteria
- Past Performance
- Bidder Turnover
- Certificate (Requested in ATC)
- OEM Authorization Certificate
- OEM Annual Turnover
- Compliance of BoQ specification and supporting document *In case any bidder is seeking exemption from Experience / Turnover Criteria
- the supporting documents to prove his eligibility for exemption must be uploaded for evaluation by the buyer
Probable Bidders
Companies likely to bid
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